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| this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. october 2003 1/34 ? STV9212 video processor for crt monitors with pictureboost ? main features n general l i2c-bus controlled l supports ac- and dc-coupled applications l 5v to 8v power supply l matches to virtually any video amplifier n pictureboost ? l pictureboost ? insertion input l full-screen pictureboost ? via i2c-bus l context-sensitive picture enhancement n video clamping l input and output video clamp l sync pulse polarity auto-rectification l clamp pulse generation timed either by sync or video blanking pulse n video processing l contrast adjustment with excellent channel matching l gain stages for control of white l two dc-mode cut-off ranges l output dc offset control l automatic beam limiter (abl) l video insertion pulse (vip), 2 levels l amplifier control (blanking and stand-by) n osd insertion with contrast control n control output l amplifier standby and blanking control l 3 dac for control of dc restore amplifier or brightness in dc-coupled system general description the STV9212 is an i2c-bus controlled color video processor designed for standard crt monitor applications. it can drive systems where cathodes are either ac- or dc-coupled to the amplifier outputs. the three video channels provide contrast and white balance separate gain adjustments as well as one-per-channel dc cut-off control and common dc offset control functions. on top of these usual controls, it features context-sensitive picture enhancement circuitry to support the pictureboost ? function that enhances the appearance of still pictures and moving video. in ac coupling applications, the device can pilot three cathode dc restore channels dedicated to set crt cut-off bias voltages and to control brightness through cathodes. the rgb video outputs have a class a architecture and directly drive the amplifier channels without unnecessarily consuming current. bandwidth limitation i2c-bus adjustments can contribute to keeping the application emi under control. osd (on-screen display) graphics are inserted by means of a fast blanking signal. independent osd contrast control facilitates adaptation to various osd generators and provides system flexib ility. the STV9212 is perfectly compatible with other st components for crt video boards, such as video amplifiers and osd generators. dip24s :(plastic package) order code: STV9212
STV9212 2/34 table of contents chapter 1 STV9212 pin allocation and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 pinout .................................................................................................................... .............. 4 1.2 pin descriptions .......................................................................................................... ........ 4 chapter 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.1 video rgb input clamp ...................................................................................................... .6 2.2 video blanking ............................................................................................................. ........ 8 2.3 contrast control stage and automatic beam limiter .......................................................... 9 2.4 pictureboost ............................................................................................................... ...... 10 2.5 osd insertion .............................................................................................................. ....... 11 2.6 drive stage ................................................................................................................ ........ 11 2.7 video insertion pulse ...................................................................................................... ... 12 2.8 output stage ............................................................................................................... ....... 12 2.9 output infra-black level, cut-off and brightness ... ............................................................ 15 2.10 signal waveforms .......................................................................................................... .... 18 2.11 miscellaneous ............................................................................................................. ....... 18 chapter 3 i2c-bus interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.1 i2c-bus register descriptions ............................................................................................ 21 chapter 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.1 absolute maximum ratings ............................................................................................... 24 4.2 thermal data ............................................................................................................... ...... 24 4.3 static electrical characteristics .......................................................................................... 24 4.4 dynamic electrical characteristics ..................................................................................... 25 4.5 i2c-bus electrical characteristics ....................................................................................... 27 4.6 i2c-bus interface timing requirements ........................................................................... 27 chapter 5 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 chapter 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 chapter 7 input/output diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3/34 STV9212 chapter 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 STV9212 pin allocation and description STV9212 4/34 1 STV9212 pin allocation and description 1.1 pinout 1.2 pin descriptions figure 1: STV9212 pinout table 1: STV9212 pin descriptions pin name function pin name function 1 in1 video input, channel 1 13 scl i2c-bus clock input 2 hs video clamp sync input 14 sda i2c-bus data input/output 3 in2 video input, channel 2 15 co3 cut-off / brightness dac 3 output 4 abl automatic beam limiter input 16 co2 cut-off dac 2 output 5 in3 video input, channel 3 17 co1 cut-off dac 1 output 6 gnda analog ground 18 out3 video output, channel 3 7 vcca analog supply 19 gndp output stage ground 8 pb picture boost input 20 out2 video output, channel 2 9 osd1 osd input, channel 1 21 vccp output stage supply 10 osd2 osd input, channel 2 22 out1 video output, channel 1 11 osd3 osd input, channel 3 23 ampctl output for amplifier control 12 fblk osd insertion control input 24 blk blanking and video clamp sync input 1 2 3 4 5 6 7 8 9 10 15 16 24 23 22 21 20 19 18 17 11 14 12 13 in1 hs in2 abl in3 gnda vcca pb osd1 osd2 osd3 fblk blk ampctl out1 vccp out2 gndp out3 co1 co2 co3 sda scl 5/34 STV9212 functional description 2 functional description the functional blocks are described in the order they act on the signal. figure 2: STV9212 block diagram blk hs vccp fblk sda scl 14 13 osd1 osd2 osd3 6 gnda 20 out2 18 out3 3 5 4 in1 in2 in3 abl 23 ampctl STV9212 vref 1 out1 + gndp i 2c 3v (dc) preamplifier stand-by eht amplifier gnd stdb/ drive 2 24 21 output channel 1 dc or ac 22 g v stage 12 fblk 17 g dc 7 vcca pb 8 co1 dcin1 dcout1 19 16 co2 15 co3 i2c blk icp, ocp 9 10 11 vout1 decoder i2c-bus standby & blanking i2c vccp blki blki i2c i2c-bus control path video/control signal path clamp blki icp icp + blki ocp ocp osd infra-black level cut-off brightness vip level channel 3 osd contrast channel 2 + contrast pictureboost functional description STV9212 6/34 2.1 video rgb input clamp the three rgb inputs have to be supplied with a video signal through coupling capacitors playing the role of analog memories for internal video clamps. the input clamping level is approximately 0v. the clamp is gated by the input clamp pulse (icp) that is internally generated from a signal on either the hs or blk pin. the selection is done via register 8 of the i2c-bus. for more information, refer to figure 3: icp, ocp and blki generation and table 2: icp timing . provided with an automatic polarity rectification function, the hs input accepts horizontal synchronization signals of either polarity. the device can select either the leading or trailing edge of this signal to trigger the icp generator. the blk input is followed by an inverter stage that can be enabled or by-passed via the i2c-bus. this allows the use of a signal of either polarity, the control software taking care of the inverter position according to the signal applied. the blki signal found behind this inverter stage also drives the video blanking circuitry which requires a positive blki polarity for correct operation. once bit blkpol has correctly been uploaded to ensure a positive blki polarity, the icp triggering edge can be selected via control bit bcedge . a horizontal flyback pulse is generally expected to be applied on the blk input. as the edges of horizontal flyback pulse can fall into the active video content (outside the video signal line blanking portion), the application must ensure that such an edge is never selected for triggering the icp. the width of the internally generated icp is controlled via the i2c-bus. the hs input can be used to pass a clamping pulse, if available in the application, directly to clamping stages, without any additional processing. in this case, the appropriate polarity (positive) is required. see table 2: icp timing . the icp timings triggered by the trailing edge of the blk signal are not presented. the output clamp pulse (ocp) is described in section 2.8: output stage . figure 3: icp, ocp and blki generation hs pulse generation blk icp (internal) ocp (internal) blkpol icp width 2 24 on -1 (sad09/b0) 0 1 bcedge -1 (sad08/b1) 0 1 0 1 automatic polarity bcsc0 (sad08/b0) pulse generation on bcwdth (sad08/b2,b3) ocpsc (sad08/b7) bcsc1 (sad08/b4) 0 1 0 1 note: the i2c-bus switches are displayed in their default positions video blanking icp trig/pulse mode blki (internal) blki i2c-bus field 7/34 STV9212 functional description table 2: icp timing trigger source trigger event bcsc1 bcsc0 bcedge blkpol timing diagram hs pin trailing edge 000 dont care leading edge 001 dont care pulse 1 dont care dont care dont care blk rising edge 01 00 11 falling edge 01 01 10 figure 4: video input clamp hs icp negative or positive 0.33s...1.33s hs icp negative or positive 0.33s...1.33s hs icp (must be positive!) blk icp 0.33s...1.33s blk icp 0.33s...1.33s in1 1 high impedance note: identical for in2 and in3 inputs stage to further processing icp input video 0v 0v 0v v ref = internal reference voltage (fixed) dc signal from clamped to gnd v ref graphics card (can vary) functional description STV9212 8/34 2.2 video blanking the three video channels are simultaneously blanked with the high level of either blki or fblk signals. blki is an internal signal drawn from the signal applied on the blk pin (h-flyback) as shown in figure 3 . the blanking consists in forcing a black level to the internal clamped video signal. blk input the blk input receives an h-flyback pulse that drives: l the video blanking circuitry during scan line retrace, l the output clamping stage. a clipping circuit at the input allows the direct use of a high-voltage h-flyback pulse applied through a serial resistor as shown in figure 5 . a logic-level signal is also accepted but the serial resistor remains mandatory. in all cases, the value of this resistor must be such that the sinking and sourcing currents are limited to 1ma and 100a, respectively. permanent blanking the entire tv screen can be blanked for an unlimited amount of time using the software blanking feature. both bits swblk and tst1 must be set to 1. the three video outputs are forced to their infra-black levels as shown in figure 6 . infra-black levels are defined in section 2.9 . figure 5: blk input pin figure 6: software blanking gnd 40 to 0 to -10v typical h-flyback signal gnd ~3v signal at blk pin (pin 24) (*) r lim is necessary to limit currents flowing through blk pin (-100ua, +1ma max.) blk r lim (*) 24 100v normal operation swblk =0, tst1 =0 software blanking in operation swblk =1, tst1 =1 black level infra-black level video output channels 1,2,3 9/34 STV9212 functional description the screen can also be blanked by permanently keeping the on-screen display fblk input signal at high level. in this case, only the video contents of the three video channels are replaced by black level osd content insertion (signals on pins osd1 through osd3 permanently at low level). refer to section 2.5: osd insertion on page 11 . 2.3 contrast control stage and automatic beam limiter the contrast stages are simultaneously controlled on all three rgb channels with high attenuation matching precision. refer to electrical specifications for values. see figure 7: contrast control and table 4: i2c-bus register map . the automatic beam limiter (abl) is an attenuator controlled through the abl input, independent of contrast stage attenuation. the operating range is about 2 v (from 3 v to 1 v). a typical characteristic is shown in figure 8 . refer to section 4: electrical specifications for specific values. when not used, the abl pin is to be connected to vcca. figure 7: contrast control figure 8: abl characteristics before contrast stage after contrast stage v ref v ref note: crst i2c-bus field acts equally on all 3 video channels video black level video black level crst =max crst =mid crst =min 5 0 -2 -4 -6 -8 -10 -12 -14 -16 attenuation (db) 0 v abl (v) 4 3 2 1 functional description STV9212 10/34 2.4 pictureboost the pictureboost ? function provides a picture enhancement effect for images with photographic or moving video contents. the function is activated whenever the level on pin pb is high (ttl) or the bit pbins is at 1, if the general pictureboost ? enable bit pbgen is at 1. by means of pb input signal toggling, the function can take effect in a part of the screen, e.g. a window, or on the whole screen. the picture enhancement is achieved through combination of three actions, as shown in figure 9 : l a content-sensitive peaking with slow restore (vivacity), l a contrast addition, l a brightness addition. the vivacity amplitude depends on the slope height and steepness and on the status of bits pbvivam[1:0] . the return to stabilized state is exponential with a time constant adjustable via bits pbvivtc[2:0] . any undershoot below the video black level is clipped to a level close to black. the pictureboost ? brightness is a dc offset superimposed on the video signal in the boosted zone. its value is selected by bits pbbrig[1:0] . the vivacity and pictureboost ? brightness are both enabled by bit pbviven . the pictureboost ? contrast component evenly increases the video amplitude in the boosted zone. its value is controlled by bits pbcrst[1:0] . refer to section 4: electrical specifications for values. figure 9: pictureboost action pb brightness h-sync video before pb input t viv v viv pb contrast pictureboost ? stage video after pictureboost ? stage clipping a a 11/34 STV9212 functional description 2.5 osd insertion the on-screen display (osd) is inserted with a high level on the fblk input (ttl). the device acts as follows: l the three rgb video input signals (in1, in2, in3) are internally blanked, i.e. put at the black level. l binary levels (ttl) on inputs osd1, osd2 and osd3, after processing in the osd contrast stage, are added to the corresponding blanked video channels. in this way, the osd contents replace the video contents where the fblk input is high. see figure 2 and figure 10 . the osd is inserted after the pictureboost ? block and before the drive block. as a consequence, osd insertion overlaps all video contents, including the pictureboost ? -ed zones. color temperature adjustments by means of the i2c-bus drive registers act in the osd insets. the osd contrast stage allows the adjustment of the level of osd insets simultaneously on the three osd channels and independently of the video contrast adjustment. refer to section 4: electrical specifications for values. 2.6 drive stage the drive stage is a set of three attenuators separately controlled via three i2c-bus registers, drive1, drive2 and drive3. it affects all signals, ordinary video, pictureboost ? processed video and osd insets. it is designed to compensate for differences in gain of the three crt cathodes. see figure 11 and for values, refer to section 4: electrical specifications . figure 10: osd insertion osd insertion fblk osd1(2,3) osd min. max signals video black level mid v osd video before osdcrst osd insertion video after v ref video black level v ref note: the osdcrst i2c-bus field acts equally on all 3 osd channels. functional description STV9212 12/34 2.7 video insertion pulse the video insertion pulse (vip) creates an indent on the three video signals, timed with the positive part of the blki signal. (see section 2.2: video blanking on page 8 ). as its level is below the video black level, it introduces a video infra-black level. the video infra-black level position versus ground is then controlled in subsequent stages. in the absence of the blanking pulse on pin blk, the vip is not inserted and the subsequent stages control the position of video black level. figure 12 shows the signal before and after insertion of the vip. two different vip values are programmable by bit vip . refer to section 4: electrical specifications for values. 2.8 output stage the output stage consists of an output clamp and a buffer. if a reduced output video am plitude and/ or a reduced infra-black level range is sufficient in the application, the v ccp can be lowered to 5v. figure 11: drive control figure 12: vip insertion before drive stage after drive stage v ref v ref one i2c-bus register drivex (x=1, 2 or 3) per video channel video black level video black level drivex =max drivex =mid drivex =min vip insertion video before blki signal video black level v ref vip insertion video after video black level v ref v vip v ref +v vip video infra-black level note: identical for video channels 1, 2 and 3. 13/34 STV9212 functional description even at 8v of v ccp , care must be taken at device application level to ensure operation without signal top limitation. 2.8.1 output clamp the dc position of video infra-black and video black levels at the video outputs must be fixed regardless of video or osd inset contents, especially in applications where the devices output infra-black level determines directly the infra-black level on the crt cathodes (dc-coupled applications). this fixing is achieved by means of a fully-integrated output clamp that brings the output video infra-black level (video black level, in absence of the blk pulse) to the level of a variable reference (v ib ) as shown in figure 13 . the v ib is described in detail in section 2.9 on page 15 . the clamp circuit is driven by the output clamp pulse (ocp). for correct operation, this pulse must entirely fall into the vip pulse if this is present (clamp of infra-black level) or onto the video black part (clamp of black level). in the former case, the ocp generator is to be triggered with the leading edge of the blk pulse, in the latter case it must copy the icp pulse. refer to figure 3 for the ocp generation block diagram. ta b l e 3 shows possible ocp timings. although possible, the ocp timings, triggered by the blk trailing edge, are not shown as they have no practical use. 2.8.2 bandwidth control controlled via bits bw[3:0] , the output stage can limit the rise and fall time of the output signal. the optimum choice for this adjustment is highly application dependent. refer to section 4: electrical specifications for values and to section 6: application hints for practical advice. 2.8.3 output buffer the output buffer provides enough current so that external buffers are not required and the power amplifier can interface directly to the devices outputs. figure 13: output stage blki output stage video before output note: identical for video channels 2 and 3. ocp out1 ocp 22 gnd v ref v ib v ib vccp 15 + - infra-black level clamp & buffer functional description STV9212 14/34 table 3: ocp timing source trigger event ocpsc blkpol timing diagram icp pulse 1 dont care blk rising edge 0 0 falling edge 1 icp ocp blk ocp blk ocp 15/34 STV9212 functional description 2.9 output infra-black level, cut-off and brightness the schematic diagram of these functions is shown in figure 14 . 2.9.1 output infra-black level the infra-black level of the video signal at the video outputs out1, out2 and out3 is positioned to the v ib reference by the output clamp circuit, thus defining the output infra-black level. if the output clamp circuit is furnished with a correctly timed ocp (see corresponding sections), the output infra-black level equals v ib . v ib is composed of a fixed dc voltage (v ibmin ), a variable dc voltage (v ibof ) applied on all three channels and a per-channel variable dc voltage (v ibl (1,2,3)) as shown in figure 15 . in ac-coupling mode (bit mod = 1), the v ibl part is suppressed and the v ib is therefore equal on all three channels, only varying with bits ibof[5:0] acting on v ibof . this can be used to match the devices outputs to the input of the video amplifier used (biasing). in dc-coupling mode (bit mod = 0), v ibl (1,2,3) are separately set via bits ibl1[7:0] , ibl2[7:0] and ibl3[7:0] , respectively. this serves to adjust the cut-off points of the three crt cathodes. in this case, v ibof can serve to pre-position the cut-off ranges in the factory adjustment procedure or/and to provide a rough brightness control. figure 14: cut-off and brightness control block diagram dc ac:1 dc:0 mod output stage v ibmin v ibldc cut-off cut-off cut-off iblrg brightness range range range ibof 1 for 3 channels 1 for 3 channels 1 per channel channel 3 brig co1 out1 v ib dc dc:0 ac:1 v ib v ref v comin note: identical for co1, co2 and co3 outputs except for brightness (v bridc ) that is only output at co3 while mod=0. v iblac v briac v bridc the switches are drawn in their default positions. v co gnd brigrg i2c-bus field ibl1 ibl2 ibl3 v co v comax v comin mod =1 mod =0 video dc level only ~40k w out2 out3 co2 co3 v iblac v briac v bridc ~0v* ch3 ch1 ch2 * ~0v when the output is left open functional description STV9212 16/34 2.9.2 cut-off and brightness control outputs outputs co1, co2 and co3 provide a dc voltage controlled via bits brig[7:0] , iblx[7:0] , iblrg[7:0] , brigrg[1:0] and mod[7:0] . the principal of operation is shown in figure 14 . when bit mod is in position ac (= 1), the output voltage is a sum of the brightness v briac , cut-off v iblac and a fixed v comin providing a bottom limitation. the brightness adjustment is equally applied to all three co1, co2 and co3 outputs. it varies depending on bits brig[7:0] and brigrg[1:0] , with bits brigrg[1:0] controlling the range of brig adju stment. the cut-off adjustment is separate for each channel, having one i2c-bus field per channel: ibl1 , ibl2 and ibl3 . the ratio between the brightness and cut-off ranges depends on the brightness range selection. see figure 16 . when bit mod is in position dc (= 0), the output voltage on co3 output is a sum of the brightness v bridc and a fixed v comin providing a pedestal. outputs co1 and co2 are floating with internal figure 15: output infra-black level figure 16: co1, co2 and co3 outputs while mod = 1 out1 22 18 20 out2 out3 19 black infra-black v ib (1) v ib (2) v ib (3) v ibmin v ibmin v ibmin v ibof v ibof v ibof v ibl (1) v ibl (2) v ibl (3) dc: differential cut-off i2c: ibl1, ibl2, ibl3 dc: common cut-off/brightness ac: video amp. biasing i2c: ibof fixed dc ac: v ibl (1,2,3) = 0v channel 1 channel 2 channel 3 gndp co1 17 15 16 co2 co3 19 v co (1) v co (2) v co (3) v comin v comin v comin v briac v briac v briac v iblac (1) v iblac (2) v iblac (3) i2c: ibl1, ibl2, ibl3 brightness through cathods i2c: brig fixed dc cut-off channel 1 channel 2 channel 3 gndp 17/34 STV9212 functional description resistors of approximately 40 k w to ground. the v bridc varies with bits brig[7:0] and does not depend on bits brigrg[1:0] . see figure 17 . figure 17: co1, co2 and co3 outputs while mod = 0 co1 17 15 16 co2 co3 19 v co (3) v comin v bridc brightness through g1 i2c: brig fixed dc channel 1 channel 2 channel 3 gndp note: channels 1 and 2 shown with co1 and co2 outputs left open functional description STV9212 18/34 2.10 signal waveforms figure 18 gives a summary of main signals waveforms. 2.11 miscellaneous 2.11.1 stand-by mode the device is set in stand-by mode either by means of bit pastby or by lowering the v ccp supply voltage below the v ccps threshold. once in stand-by mode, the device does not process the video signal and its power consumption is significantly reduced. the i2c-bus interface remains operational. a low level is forced on the ampctl output. refer to section 4: electrical specifications for values. 2.11.2 ampctl output the ampctl is designed to control a video power amplifier. it provides a three-level logical signal that depends on bits astby and ablen , as well as on the operating mode (stand-by / normal) of the device. figure 19 gives all possible states of the ampctl output. refer to section 4: electrical specifications for electrical parameter values. pin ampctl is of push-pull type. it must not directly figure 18: signal waveforms hs icp blki video input fblk osd input video output osd signals black-level infra-black control signals ocp clamp signals level in1 (2,3) osd1 (2,3) out1 (2,3) 19/34 STV9212 functional description be grounded in the application and it can be left floating. only video amplifiers provided with an appropriate control input can take advantage of the signal on the ampctl output. figure 19: ampctl output states blki signal ampctl pin signal gnd v ampsb v ampbl v amphi astby pastby ablen v ccp x 1 x >v stbth 1 x x >v stbth >v stbth 21/34 STV9212 i2c-bus interface specifications 3.1 i2c-bus register descriptions sad01 read/write reset value: 1000 0000 (80h) values 00 and 7fh in field crst[6:0] are prohibited. bits[7:1] = contrast adjustment ( crst ) bit 0 = reserved sad02 read/write reset value: 1000 0000 (80h) bits[7:0] = brightness adjustment (brig) in ac mode, this value is added to infra- black levels and output on pins co1, co2 and co3. in dc mode, it is output all alone on pin co3. sad03 read/write reset value: 1000 0000 (80h) values 00 and 7fh in field drive1[6:0] are prohibited. bits[7:1] = gain adjustment on channel 1 ( drive1) bit 0 = reserved sad04 read/write reset value: 1000 0000 (80h) values 00 and 7fh in field drive2[6:0] are prohibited. bits[7:1] = gain adjustment on channel 2 ( drive2 ) bit 0 = reserved sad05 read/write reset value: 1000 0000 (80h) values 00 and 7fh in field drive3[6:0] are prohibited. bits[7:1] = gain adjustment on channel 3 ( drive3) bit 0 = reserved. sad06 read/write reset value: 0000 0001 (01h) bits[7:2] = reserved. bits[1:0]= brightness adjustment range (brigrg) four positions. see section 4.4: dynamic electrical characteristics . sad07 read/write reset value: 0000 1001 (09h) bits[7:4] = reserved. bits[3:0]= osd contrast adjustment sad08 read/write reset value: 0000 0100 (04h) bit 7 = output clamping pulse selection 0: pulse triggered by blk input (default) 1: internal icp pulse 70 crst[6:0] 70 brig[7:0] 70 drive1[6:0] 70 drive2[6:0] 70 drive3[6:0] 70 brigrg [1:0] 70 osdcrst[3:0] 70 ocpt g tst[1:0] bcsc 1 bcwdth[1:0] bced ge bcsc 0 i2c-bus interface specifications STV9212 22/34 bits[6:5] = test mode activation for device testing in fabrication. when performing software blanking through swblk bit, tst1 bit must be set to 1. 0: normal operation mode (default) 1: test mode bits[4,0] = blanking and clamping pulse source. bits[3:2] = width of icp pulse when bit bcsc1 is 0. bit 1 = when hs pin is selected to trigger the icp pulse generator. 0: trailing edge of hs pulse (default) 1: leading edge of hs pulse when blk pin is selected to trigger the icp pulse generator: refer to blkpol bit description. sad09 read/write reset value: 0001 0000 (10h) bit 7 = amplifier standby selection. 0: normal (default) 1: standby bit 6 = amplifier blanking enable. the bit is dont care whenever bit astby is in standby position. 0: blanking pulse not generated (default) 1: blanking pulse generated bit 5 = reserved. bit 4 = test mode activation for device testing in fabrication. 0: test mode 1: normal operation mode (default) bit 3 = reserved. bit 2 = application mode selection. 0: application with dc-coupled cathodes. (default) 1: application with ac-coupled cathodes. bit 1 = permanent blanking of video channels through software. 0: disable, blanking gated with signal on blk pin. (default) 1: permanent blanking. bit tst1 must also be set to 1. bit 0 = blanking signal (h-fly back) polarity inversion. for correct operation, the internal blki pulse after this controlled inversion must be positive. 0: non inverted, good for positive blanking pulse (default) 1: inverted, good for negative blanking pulse sad0a, sad0b and sad0c read/write reset value: 1000 0000 (80h) bits[7:0] = infra-black (cut-off) level control, channels 1 to 3 (iblx) in dc-coupling mode, the register controls the pedestal of corresponding video channel signal. in ac-coupling mode, the register controls the level on outputs co1, co2 or co3, respectively. sad0d read/write reset value: 0000 1000 (08h) bit 7 = preamplifier and amplifier standby selection 0: normal (default) 1: standby bit 6 = reserved. bcsc1 bcsc0 selected source 0 0 hs pin trigger (default) 0 1 blk pin trigger 1 dont care hs pin pulse bcwdth bcpc width 0 0 0.33 s 0 1 0.66 s (default) 10 1s 1 1 1.33 s bcedge blkpol trigger on blk 0 0 rising edge (default) 0 1 falling edge 1 0 falling edge 1 1 rising edge 70 astb y able n tst2 mod swbl k blkp ol 70 ibl1[7:0] ibl2[7:0] ibl3[7:0] 70 past by tst[4:3] bw[3:0] 23/34 STV9212 i2c-bus interface specifications bits[5:4] = test mode activation bits for device testing in fabrication. 0: normal operation mode (default) 1: test mode bits[3:0] = internal band width limitation control. refer to electrical characteristics. sad0e read/write reset value: 1100 0001 (c1h) bit 7 = video insertion pulse depth. 0: 0.2v 1: 0.4v (default) bits[6:1] = infra-black level offset control simultaneously on all three video channels. bit 0 = control range of infra-black level adjustments via ibl1 , ibl2 and ibl3 registers. acts either on video signal channels or co1, co2, co3 outputs. refer to electrical characteristics. 0: wide 1: narrow (default) sad0f read/write reset value: 0000 1001 (09h) bit 7 = pictureboost general enable. (pbgen) 0: disable, function inhibited (default) 1: enable, function active bit 6 = pictureboost insertion control. (pbins) 0: pb pin insertion (default) 1: permanent insertion regardless of signal on pb pin bit 5 = reserved. bits[4:3] = pictureboost contrast control (pbcrst) bit 2 = reserved. bits[1:0] = pictureboost brightness control (pbbrig) sad10 read/write reset value: 0010 1000 (28h) bit 7 = pictureboost vivacity and brightness enable. 0: disable (default) 1: enable bits[6:5] = pictureboost vivacity amplitude control. bit 4 = reserved. bits[3:1] = pictureboost vivacity time constant control. bit 0 = reserved. 70 vip ibof[5:0] iblr g 70 pbge n pbin s pbcrst[1:0] pbbrig[1:0] 70 pbviv en pbvivam[1:0] pbvivtc[2:0] electrical specifications STV9212 24/34 4 electrical specifications 4.1 absolute maximum ratings all voltages refer to the gnda pin. 4.2 thermal data 4.3 static electrical characteristics t amb = 25c, v cca = 5v, and v ccp = 8v, unless otherwise specified. all voltages refer to the gnda pin. symbol parameter min. max. units v cca supply voltage on vcca (pin 7) tbd 5.5 v v ccp supply voltage on vccp (pin 21) tbd 8.8 v v in voltage at any pin except video inputs and supply pins tbd 5.5 v v i voltage at video inputs (pins 1,3 and 5) tbd 1.4 v v esd esd susceptibility human body model (100 pf discharge through 1.5 k w ) tbd 2 kv t stg storage temperature -40 +150 c t oper operating junction temperature -40 +150 c symbol parameter min. typ. max. units r thja junction-to-ambient thermal resistance 60 c/w t amb operating ambient temperature 0 70 c/w symbol parameter test conditions min. typ. max. units supply v cca supply voltage pin 7 4.5 5 5.5 v v ccp power stage supply voltage pin 21 4.5 8 8.8 v v ccps power supply voltage stand-by threshold pin 21 2.5 3.0 3.5 v i cca vcca supply current v cca = 5v ( pbgen disable) v cca = 5v ( pbgen enable) 65 85 ma ma i ccp vccp supply current v ccp = 8v 50 ma i s total supply current in stand-by mode pin 21 and pin 7 6 ma inputs and outputs v i video input voltage amplitude 0.7 1 v v o output voltage swing 0.5 ( 1 ) v ccp -0.5v v v il low level input voltage (ttl) osd, fblk, pb, hs,blk 0.8 v v ih high level input voltage (ttl) osd, fblk, pb, hs,blk 2.4 v i il blk input current blk -0.1 +1.0 ma i in input current osd, fblk, pb -1 1 a 25/34 STV9212 electrical specifications 4.4 dynamic electrical characteristics t amb = 25c, v cca = 5 v, v ccp = 8 v, v i = 0.7 v pp , c load = 5 pf, r s = 100 w serial resistor between output pin and c load , unless otherwise specified. x denotes channel number and can assume values of 1, 2 and/or 3. all voltages refer to the gnda pin. r hs input resistance hs 40 k w v ampsb output voltage at ampctl pin, standby ( figure 18 ) i2c-bus bit astby = 1 or/and v ccp < v ccps sink current 200a 80 200 mv v ampbl output voltage at ampctl pin, blanking ( figure 18 ) i2c-bus bit astby = 1 i2c-bus bit ablen = 1 sink current 0a blki at high level tbd 1.6 tbd v v amphi output voltage at ampctl pin, no standby, no blanking ( figure 18 ) i2c-bus bit astby = 0 and v ccp > v ccps sink current 0a 3.1 v symbol parameter test conditions min. typ. max. units video output signal (pins 18, 20 and 22) - contrast and drive g maximum total gain for video path with pictureboost off i2c-bus fields crst = 7eh, drivex =7eh pbgen = 0 12 db v om maximum video output voltage ( 2 ) i2c-bus fields crst = 7eh, drivex =7eh pbgen = 0 pbgen = 1 2.8 4.0 v v v on nominal video output voltage i2c-bus fields crst = 40h, drivex = 40h (por state) tbd v car contrast control range max. to min. contrast ( crst = 7eh to crst = 01h) 28 db dar drive control range max. to min. drive ( drivex = 7eh to drivex = 01h) 13 db gm gain matching ( 3 ) i2c-bus fields crst = 40h, drivex = 40h (por state) 0.1 db video output signal - osd v osd osd insertion output level referenced to output black level drivex = 7eh osdcrst = 0fh osdcrst = 0h 4.9 0 v v video output signal - vip v vip video insertion pulse level from infrablack level to black level vip = 1 vip = 0 ( 4 ) 0.4 0.2 vpp vpp video output signal - infra black level ( figure 15 ) v ibmin infra black level pedestal 0.4 v v ibof infra black offset component ibof = 3fh ibof = 0h 2.1 0 v v v ibl [x] infra black level component ibl x = 0h or mod = 1 (ac mode) ibl x = ffh, mod = 0 (dc mode) iblrg = 1 iblrg = 0 0 1.3 1.8 v v v symbol parameter test conditions min. typ. max. units electrical specifications STV9212 26/34 cut-off output (pins co1, co2 and co3) v comin pedestal level on cox outputs 0.5 v v comax upper limitation on cox outputs sum of v briac +v iblac or v bridc exceeding the limit v cca -0.5v v v briac brightness component in ac mode ( figure 16 ) mod = 1 (ac mode) brig = 0h brig = ffh: brigrg = 00b brigrg = 01b brigrg = 10b brigrg = 11b 0 0.4 0.8 1.25 1.9 v v v v v v bridc brightness component in dc mode on co3 pin ( 6 ) ( figure 17 ) mod = 0 (dc mode) brig = 0h brig = ffh 0 4 v v v iblac (x) cut-off component mod = 0 (dc mode) mod = 1 (ac mode) iblx = 0h iblx = ffh: iblrg = 0 iblrg = 1 0 0 3.7 1.85 v v v v pictureboost ? block ( figure 9 ) g pb maximum gain pbgen = 1 pbcrst = 00b pbcrst = 01b pbcrst = 10b pbcrst = 11b 0.8 1.6 2.3 3 db db db db v bripb pictureboost brightness expressed in equivalent input level pbgen = 1 and pbviven = 1 pbbrig = 00b pbbrig = 01b pbbrig = 10b pbbrig = 11b 64 48 32 16 mv mv mv mv v viv /a vivacity amplitude as percentage of its host square pulse level before pictureboost(a in figure 9 ) pbgen = 1 and pbviven = 1 pbvivam = 00b pbvivam = 01b pbvivam = 10b pbvivam = 11b 12.5 25 37.5 50 % % % % t viv vivacity time constant pbgen = 1 and pbviven = 1 pbvivtc = 000b pbvivtc = 001b pbvivtc = 111b 0 35 245 ns ns ns abl ( figure 9 ) g abl abl gain v abl >3.2 v v abl = 1 v 0 -15 db db v thabl abl threshold voltage 3 v i abl abl input current v abl = 3.2v v abl = 1v 0 -2 a a video output signal - dynamic performances ( figure 15 ) t r , t f rise time, fall time ( 5 ) v out = 2v pp (vip exclusive) bw = 0fh bw = 00h 3.5 7 ns ns bw large signal bandwidth v out = 2v pp , sinus wave, -3db bw = 0fh bw = 00h tbd tbd mhz mhz symbol parameter test conditions min. typ. max. units 27/34 STV9212 electrical specifications 4.5 i2c-bus electrical characteristics t amb = 25 c, v cca = 5 v, v ccp = 8 v, v i = 0.7 v pp , c load = 5 pf 4.6 i2c-bus interface timing requirements notes on electrical characteristics note 1. the video on the preamplifier output must remain above 0.5v even for high frequency signals. 2. assuming that the video output signal remains inside the linear area of the preamplifier output (between 0.5v and v ccp - 0.5v). ct crosstalk between video outputs v out = 2v pp f = 10 mhz f = 50 mhz tbd tbd db db symbol parameter test conditions min. typ. max. unit s v il low level input voltage on pins sda, scl 1.5 v v ih high level input voltage 3 v i in input current (pins sda, scl) 0.4 v < v in < 4.5 v -10 +10 a f scl(max.) scl maximum clock frequency 200 khz v ol low level output voltage sda pin when ack sink current = 6ma 0.6 v symbol parameter min. typ. max. units t buf time the bus must be free between two accesses 1300 ns t hds hold time for start condition 600 ns t sup set-up time for stop condition 600 ns t low the low period of clock 1300 ns t high the high period of clock 600 ns t hdat hold time data 300 ns t sudat set-up time data 250 ns t r rise time of both sda and scl 1 s t f fall time of both sda and scl 300 ns figure 20: i2c-bus timing diagram symbol parameter test conditions min. typ. max. units t hdat t sudat t low t high t hds t sup t buf sda scl electrical specifications STV9212 28/34 3. matching measured between the different outputs. 4. when the blanking signal is present on the blk input, the vip insertion pulse is always generated. only its amplitude changes (see figure 12 ). 5. t r , t f are simulated values, assuming an ideal input signal with rise/fall time = 0.1 ns. measured between 10% and 90% of the pulse height. 6. when mod = 0, the co1 and co2 are internally grounded through resistors. 29/34 STV9212 soldering information 5 soldering information the device can be soldered by wave, dipping or manually. wave soldering is the preferred method for mounting through-hole mount ic packages on a printed-circuit board. soldering by dipping or by solder wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joints for more than 5 seconds.the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg [max]). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. manual soldering apply the soldering iron (24 v or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may last up to 5 seconds. package mechanical data STV9212 30/34 6 package mechanical data figure 21: 24-pin plastic dual in-line package, shrink 300-mil width table 5: package dimensions dim. millimeters inches min. typ. max. min. typ. max. a 5.08 0.200 a1 0.51 0.020 a2 3.05 3.30 4.57 0.120 0.130 0.180 b 0.38 0.46 0.56 0.015 0.018 0.022 b2 0.89 1.02 1.14 0.035 0.040 0.045 c 0.23 0.25 0.38 0.009 0.010 0.015 d 22.35 22.61 22.86 0.880 0.890 0.900 e 7.62 8.64 0.300 0.340 e1 6.10 6.40 6.86 0.240 0.252 0.270 e 1.78 0.070 ea 7.62 0.300 eb 10.92 0.430 ec 0.00 1.52 0.000 0.060 l 2.54 3.30 3.81 0.100 0.130 0.150 number of pins n24 stand -o ff be b2 d 13 12 24 1 ea c e1 e eb eb ec e l a a2 a1 e1 0.015 in. 0.38 mm. gage plane 0.015 in. 31/34 STV9212 input/output diagrams 7 input/output diagrams figure 22: video inputs figure 23: abl input figure 24: amplifier control output high impedance in1 30k 1 v cca gnda idem for pads in2 (3) and in3 (5) abl 1k 4 v cca gnda ampctl 100 23 gnda v cca figure 25: hsync input figure 26: pictureboost and osd inputs figure 27: analog supplies gnda gndl 2 v cca osd1 gnda gndl v cca 9 idem for pads osd2 (10), osd3 (11) pb (8), fblk (12) gnda logic part (8v) v cca 7 6 input/output diagrams STV9212 32/34 figure 28: i2c-bus figure 29: output stage supply and video outputs figure 30: blanking / video clamping sync inputs (8v) 30k w 4pf 4pf gndl gndl gnda gnda scl sda 30k w 13 14 out1 gndp (20v) gnda v ccp 19 22 idem for pads out2 (20) and out3 (18) blk gnda gndl v cca 24 figure 31: output stage ground figure 32: cut-off dac output pins gnda v cca 19 gndp co1 gnda v cca idem for pads co2 (16) and co3 (15) 17 33/34 STV9212 revision history 8 revision history table 6: summary of modifications version date description 1.0 14 nov 2002 first issue 1.1 03 jul 2003 minor modifications. STV9212 34/34 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com |
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